1. Field of the Invention
The present invention relates to a transistor-bias voltage stabilizing circuit for stabilizing the bias voltage of a field-effect transistor or a bipolar transistor employed in typically a monolithic microwave integrated circuit.
2. Description of the Prior Art
A monolithic microwave integrated circuit (referred to hereafter simply as an MMIC) employing a field-effect transistor (referred to hereafter simply as an FET) or a bipolar transistor made of a compound semiconductor such as gallium arsenide has an excellent frequency characteristic and generates only a small amount of noise. For these reasons, the MMIC is widely used in a mobile communication apparatus, a representative of high-frequency systems. Since how to make the characteristics of devices employed in such a high-frequency system uniform with ease is one key point for cost reduction, an adjustmentless feature of an integrated circuit (referred to hereafter simply as an IC) is desirable. From a standpoint of guaranteeing an operation time, that is, a standpoint of usage freedom, the assurance of stable characteristics of the IC against variations in power-supply voltage is indispensable.
Taking an MMIC employing an FET as an example, the adjustmentless feature of an IC and the assurance of stable characteristics of the IC against variations in power-supply voltage are explained by referring to FIGS. 1 to 4. FIG. 1 is a diagram showing the configuration of a representative circuit of a one-stage amplifier manufactured as an MMIC. As shown in the figure, the MMIC 10 comprises an input terminal 1 for receiving a radio-frequency (referred to hereafter simply as RF) input signal, an output terminal 2 for supplying an RF output signal to an external circuit, an FET 3 made of a compound semiconductor such as gallium arsenide, an input matching circuit 4 provided between the input terminal 1 and the gate of the FET 3 for obtaining a gain in a desired frequency band and input-impedance matching and an output matching circuit 5 provided between the output terminal 2 and the drain of the FET 3 for obtaining a gain in a desired frequency band and output-impedance matching. A voltage V.sub.dd ' of a power supply is applied to the drain of the FET 3 by way of a portion of the output matching circuit 5. On the other hand, a direct-current gate bias voltage V.sub.gg is applied to the gate of the FET 3 by way of a portion of the input matching circuit 4.
In the case of the MMIC 10 shown in FIG. 1, the direct-current gate bias voltage V.sub.gg needs to be adjusted for each MMIC 10 in order to stabilize the IC operating current against variations in threshold voltage occurring in the FET 3 and, thus, to make the frequency characteristic of the IC uniform. For this reason, in the case of the related art, typically, a bias voltage-adjustment eliminating circuit 20 like the one shown in FIG. 2 is provided separately from the MMIC 10 on the circuit board on which the MMIC 10 is mounted.
As shown in FIG. 2, the bias voltage-adjustment eliminating circuit 20 comprises a PNP-type bipolar transistor 21, a resistor R.sub.1, the terminals of which are connected to the base of the transistor 21 and a voltage V.sub.dd of the power supply respectively, a resistor R.sub.2, the terminals of which are connected to the base of the transistor 21 and the ground respectively, a resistor Re, the terminals of which are connected to the emitter of the transistor 21 and the voltage V.sub.dd of the power supply respectively, and a resistor R.sub.c, the terminals of which are connected to the collector of the transistor 21 and to the ground respectively. The emitter of the transistor 21 is connected to an input terminal of the MMIC 10 shown in FIG. 1 for receiving the voltage V.sub.dd ' of the power supply in order to supply the voltage V.sub.dd ' of the power supply to the MMIC 10. On the other hand, the collector of the transistor 21 is connected to the gate of the FET 3 shown in FIG. 1 in order to provide the direct-current gate bias voltage V.sub.gg to the FET 3.
The bias voltage-adjustment eliminating circuit 20 shown in FIG. 2 stabilizes the bias voltage of the FET 3 by feeding back a voltage drop along the resistor R.sub.e. With this bias voltage-adjustment eliminating circuit 20, the voltage drop along the resistor R.sub.e increases when the drain current of the FET 3 increases. As a result, the collector potential of the transistor 21, that is, the direct-current gate bias voltage V.sub.gg of the MMIC 10 goes down, suppressing the increase in drain current occurring in the FET 3.
However, the bias voltage-adjustment eliminating circuit 20 shown in FIG. 2 which is provided on the circuit board separately from the MMIC 10 gives rise to a problem that the number of components increases and the area for mounting components on the circuit board becomes larger.
In order to solve this problem, an MMIC 30 with a configuration adopting a self-bias voltage technique like the one shown in FIG. 3 is thought of. As shown in the figure, the MMIC 30 is the MMIC 10 shown in FIG. 1 wherein the source of the FET 3 is connected to the ground through a circuit comprising a resistor R.sub.s and a by-pass capacitor C.sub.s which are connected to each other in parallel. It should be noted, however, that the voltage V.sub.dd is used directly as a power-supply voltage of the MMIC shown in FIG. 3. Let us assume that the direct-current gate bias voltage V.sub.gg supplied to the MMIC 30 is fixed. The drain current I.sub.dd may vary from FET to FET due to variations in threshold voltage V.sub.th thereof. Since a negative feedback is added to the voltage V.sub.gs between the source and the gate of the FET 3, however, the change in drain current can be reduced in comparison with that occurring in the MMIC 10 shown in FIG. 1 without the bias voltage-adjustment eliminating circuit 20 shown in FIG. 2.
It should be noted, however, that the circuit shown in FIG. 3 has the following shortcoming. That is to say, the presence of the resistor R.sub.s reduces the voltage V.sub.ds between the source and the drain of the FET 3. Therefore, if the resistance of the resistor R.sub.s is increased in order to increase the stability of the drain current I.sub.dd, the decrease in voltage V.sub.ds between the source and the drain also becomes greater, giving rise to a problem that it is feared that the frequency characteristic of the FET 3 changes accordingly. It is thus obvious that there is a tradeoff between maintaining the voltage V.sub.ds between the source and the drain of the FET 3 and increasing the stability of the drain current I.sub.dd. As a result, it is thus impossible to completely eliminate fluctuations in drain current I.sub.dd.
A circuit shown in FIG. 4 is used as a circuit for generating the direct-current gate bias voltage V.sub.gg of an FET 33 employed in the MMIC 30 shown in FIG. 3. As shown in FIG. 4, the circuit comprises a resistor R.sub.3, one end of which is connected to the voltage V.sub.dd of the power supply, and a resistor R.sub.4, the terminals of which are connected to the other end of the resistor R.sub.3 and the ground respectively. The connection point between the resistors R.sub.3 and R.sub.4 is connected to the gate of the FET 33 shown in FIG. 3, supplying the direct-current gate bias voltage V.sub.gg to the gate of the FET 33. If the bias voltage adjustment is eliminated by supplying the direct-current gate bias voltage V.sub.gg generated by the circuit shown in FIG. 4 to the gate of the FET 33, however, fluctuations in power-supply voltage V.sub.dd result in variations in direct-current gate bias voltage V.sub.gg. As a result, it is more difficult to stabilize the drain current I.sub.dd.
As described above, in order to implement an MMIC that is not affected by changes in drain current I.sub.dd due to variations in FET characteristics and fluctuations in power-supply voltage, an externally added component must be added. An MMIC having an adjustmentless feature without using an external component has not been reported so far.